MICRO’26
KAIROS: Fast Microarchitectural Design Space Exploration by Bridging Architectural Semantics and Logic Gates
IEEE/ACM International Symposium on Microarchitecture (MICRO) · Athens, Greece · Oct 31 – Nov 4, 2026 · To appear
Computer architecture & machine learning
Hao Zheng
Electrical & Computer Engineering/University of Central Florida
Building Scalable, Efficient, and Adaptive Computing Infrastructure for AI: From Silicon to Algorithms
- AEiC, IEEE Trans. on Computers
- Director, iCAT Lab
About
Hao Zheng is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, where he directs the iCAT lab.
He received his Ph.D. from George Washington University, advised by Prof. Ahmed Louri. His research interests are in computer architecture and machine learning, with emphasis on AI/ML systems, hardware accelerators, on- and off-chip communication, manycore processors, chiplet-based systems, and AI-assisted chip design. His work has been published in top-tier computer architecture and EDA conferences and journals such as ISCA, MICRO, HPCA, DAC, ICCAD, DATE, TPDS, and TETC.
He is a recipient of the NSF CAREER Award and the UCF Reach for the Stars Award. He has served on organizing and technical program committees for top computer systems conferences and as a panelist for multiple NSF programs. He currently serves as Associate Editor-in-Chief for IEEE Transactions on Computers and as an Associate Editor for IEEE Transactions on Sustainable Computing.
If you are interested in serving as a reviewer for IEEE TC, please fill out the reviewer form.
Selected work
Selected Recent Publications
The complete list, with PDFs and code, is on the publications page.
Joining iCAT
Graduate research and teaching assistantships are available for prospective Ph.D. students. If the work here interests you, send a CV and transcripts using the contact link.
Publications
Papers, journals, and patents
Venues marked in amber are top-tier computer science conferences as listed on csrankings.org. Search by title, author, or venue.
2026
MICRO’26
Argus: An Efficient Accelerator Design for Sparse Nonlinear Solver
IEEE/ACM International Symposium on Microarchitecture (MICRO) · Athens, Greece · Oct 31 – Nov 4, 2026 · To appear
MICRO’26
DireLeak: Cross-socket Cache Timing Channels Exploiting Memory Directory
IEEE/ACM International Symposium on Microarchitecture (MICRO) · Athens, Greece · Oct 31 – Nov 4, 2026 · To appear
MICRO’26
MOSAIC: An Accelerator Design for Heterophilic Graph Learning
IEEE/ACM International Symposium on Microarchitecture (MICRO) · Athens, Greece · Oct 31 – Nov 4, 2026 · To appear
ISCA’26
TensorPrism: Rethinking Sparse High-order Tensor Acceleration via Co-occurrence Graph
ACM/IEEE International Symposium on Computer Architecture (ISCA) · Raleigh, NC · Jun 27 – Jul 1, 2026
DAC’26
PanGaea: A Unified Memory-Efficient Accelerator for Pangenome Chaining and Alignment
Design Automation Conference (DAC) · Long Beach, CA · Jul 2026
HPCA’26
Scaling Graph Neural Network Training via Geometric Optimization
IEEE International Symposium on High-Performance Computer Architecture (HPCA) · Sydney, Australia · Jan 2026
NeuS’26
Neuro-Symbolic Safety Guidance for Vision-Language-Action Models via Constrained Flow Matching
International Conference on Neuro-Symbolic Systems (NeuS) · Los Angeles, CA · Jun 16–18, 2026
2025
NeurIPS’25
GAMMA: Gated Multi-hop Message Passing for Homophily-Agnostic Node Representation in GNNs
Annual Conference on Neural Information Processing Systems (NeurIPS) · San Diego, CA · Dec 2–7, 2025
MICRO’25
Rethinking Tiling and Dataflow for SpMM Acceleration: A Graph Transformation Framework
IEEE/ACM International Symposium on Microarchitecture (MICRO) · Seoul, South Korea · Oct 2025
ISCA’25
DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference
ACM/IEEE International Symposium on Computer Architecture (ISCA) · Tokyo, Japan · Jun 2025
HPCA’25
I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators
IEEE International Symposium on High-Performance Computer Architecture (HPCA) · Las Vegas, NV · Mar 2025
2024
MICRO’24
SCALE: A Structure-Centric Accelerator for Message Passing Graph Neural Networks
IEEE/ACM International Symposium on Microarchitecture (MICRO) · Austin, TX · Nov 2–6, 2024
ICCAD’24
CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation
ACM/IEEE International Conference on Computer-Aided Design (ICCAD) · New Jersey, USA · Oct 2024
ISCA’24
MetaLeak: Uncovering Side Channels in Secure Memory Architectures Exploiting Metadata
51st International Symposium on Computer Architecture (ISCA) · Buenos Aires, Argentina · Jun 29 – Jul 3, 2024
DAC’24
EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization
61st Design Automation Conference (DAC) · San Francisco, CA · Jun 23–27, 2024
DAC’24
IPDPS’24
Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks
IEEE International Parallel & Distributed Processing Symposium (IPDPS) · San Francisco, CA · May 27–31, 2024
TPDS
Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration
IEEE Transactions on Parallel and Distributed Systems · 2024
ASP-DAC’24
Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms
ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) · Tokyo, Japan · Jan 22–25, 2024
2023
ICCD’23
Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration
IEEE International Conference on Computer Design (ICCD) · Washington, DC · Nov 6–8, 2023
ICCAD’23
ARIES: Accelerating Distributed Training in Chiplet-based Systems via Flexible Interconnects
International Conference on Computer-Aided Design (ICCAD) · San Francisco, CA · Oct 29 – Nov 2, 2023
ICCAD’23
SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-optimal Workload Balance
International Conference on Computer-Aided Design (ICCAD) · San Francisco, CA · Oct 29 – Nov 2, 2023
ICCAD’23
Path-based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications
International Conference on Computer-Aided Design (ICCAD) · San Francisco, CA · Oct 29 – Nov 2, 2023
DAC’23
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications
60th Design Automation Conference (DAC) · San Francisco, CA · Jul 9–13, 2023
ISCA’23
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations
50th International Symposium on Computer Architecture (ISCA) · Orlando, FL · Jun 17–21, 2023
GLSVLSI’23
Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework
33rd ACM Great Lakes Symposium on VLSI (GLSVLSI) · Jun 5–7, 2023
FCCM’23
OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference (Poster)
31st IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · Marina Del Rey, CA · May 8–11, 2023
TSUSC
Morph-GCNX: A Universal Architecture for High-performance and Energy-efficient Graph Convolutional Network Acceleration
IEEE Transactions on Sustainable Computing · 2023
JCST
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators
Journal of Computer Science and Technology · Feb 2023
2022
TCAS-I
ASCEND: A Scalable and Energy-Efficient DNN Accelerator with Photonic Interconnects
IEEE Transactions on Circuits and Systems I — Special Issue on Circuits and Systems for Emerging Computing Paradigms · Apr 2022
GLSVLSI’22
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation
32nd ACM Great Lakes Symposium on VLSI (GLSVLSI) · Jun 6–8, 2022
DATE’22
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems
25th Design, Automation & Test in Europe Conference (DATE) · Mar 14–23, 2022
2018 – 2021
TPDS
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing
IEEE Transactions on Parallel and Distributed Systems — Special Section on Parallel and Distributed Computing Techniques for AI, ML, and DL · 2021
TSUSC
SecureNoC: A Learning-enabled, High-performance, Energy-efficient, and Secure On-chip Communication Framework Design
IEEE Transactions on Sustainable Computing · 2021
HPCA’21
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architecture
27th IEEE International Symposium on High-Performance Computer Architecture (HPCA) · Seoul, South Korea · Feb 27 – Mar 3, 2021
DAC’20
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures
57th Design Automation Conference (DAC) · Virtual · Jul 19–23, 2020
TETC
Agile: A Learning-enabled Power and Performance-Efficient Network-on-Chip Design
IEEE Transactions on Emerging Topics in Computing (TETC) · Jun 2020 · DOI 10.1109/TETC.2020.3003496
IEEE Micro
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-On-Chip Architecture
IEEE Micro — Special Issue on Machine Learning for Systems · Sep/Oct 2020
DAC’19
An Energy-Efficient Network-on-Chip Design using Reinforcement Learning
56th Design Automation Conference (DAC) · Las Vegas, NV · Jun 2–6, 2019
CAL
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable On-chip Interconnect
IEEE Computer Architecture Letters (CAL) · vol. 17, no. 1, pp. 88–91 · 2018
Patents
US 11502934 B2
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs
U.S. Patent · Granted Nov 2022
US 11489788 B2
A Versatile and Flexible Interconnection Network Design for Chiplet-Based Manycore Architecture
U.S. Patent · Granted Nov 2022
63/019,720
Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework
U.S. Patent · Granted Jan 2025
63/665,776
Versatile Accelerator Design for Multiple Deep Neural Network Applications
U.S. Patent · Filed Jul 2024 · Pending
No publications match that search.
iCAT
Intelligent Computer Architecture
and Technology Laboratory
UCF has strong graduate programs in computer engineering. Per CSRankings, UCF stands at No. 15 in the U.S. in computer architecture and No. 5 in EDA; the computer engineering program ranked No. 50 in the 2023 U.S. News & World Report. Lab members have gone on to academia and industry — NUAA, Apple, AMD, and quantitative finance — within a short time of graduating.
For prospective students
Students at iCAT get a well-rounded grounding in computer systems and machine learning design: theory, modeling and simulation, performance evaluation, and physical implementation. You will collaborate with researchers across the country and work on industry-scale projects that turn our research into real products. Every student is supported for conference travel each year.
The lab culture is supportive and inclusive. We care about your growth, your health, and where you go next. The mentoring philosophy is simple: give you every resource you need to do work that matters, while making sure you actually enjoy the Ph.D. Every student is different, and your perspective counts.
Successful candidates are motivated, willing to learn new concepts, and want to work at the frontier of this field. We expect:
- ResearchSolid understanding or prior experience in one or more of: computer architecture, algorithms, machine learning applications, FPGA/HLS programming, or computer and mathematical modeling.
- ToolsProficient programming skills — C/C++, Python, Verilog, and scripting languages.
- ScopeOur projects cover the whole computing stack, from algorithm to silicon, so students with different backgrounds are all welcome.
Graduate research and teaching assistantships are available for prospective Ph.D. students. Send your CV and transcripts using the contact link.
Ph.D. students
-
Shilin Tian
Dean's Dissertation Fellowship · ORC Fellowship
-
Amir Ghazizadeh
-
Fangzhou Ye
ECE Best Graduate Researcher Award · FFL Fellowship · ORC Fellowship
Undergraduate researchers
-
Peyton Barnes
-
Eren Siegman
AMD Fellowship
Alumni
- Lingxiang Yin — Ph.D. 2024Associate Professor (with tenure), NUAA
- Jiaqi Yang — Ph.D., co-advisedAssociate Professor (with tenure), Shandong University
- Andres Graterol — M.S., Fall 2023 – Spring 2024UCF
- Chase Szafranski — B.S., Spring 2022 – Spring 2024AMD Fellowship · UCF
- Grace Tuomala — B.S., Fall 2023 – Spring 2024AMD Fellowship · UCF
- Mariam Rabadi — B.S., Spring 2022 – Fall 2023AMD Fellowship · UCF
- John Gierlach — B.S., Spring 2023AMD Fellowship · UCF
- Luis Infante — B.S., Fall 2024 – Spring 2025UCF
- Jessica Morris — B.S., Fall 2024 – Spring 2025UCF
- Aneesha Nayak — B.S., Fall 2024 – Spring 20252025 Order of Pegasus, the highest UCF student award
- Jaden Jeudy — B.S., Fall 2024 – Spring 2025UCF
- Briana Thakkar — B.S., Fall 2024 – Spring 2025UCF
- Jhon Tabio — B.S., Fall 2024 – Spring 2025UCF
- Sean Zarobsky — B.S., Fall 2024 – Spring 2025UCF
Research support
Teaching
Courses at UCF
Be a responsible educator.
EEL 4768
Computer Architecture
Undergraduate · Fall 2021 – Spring 2025
EEL 6938
Computer Architecture for AI/ML
Graduate · Spring 2024, Fall 2025
Course materials
Enrolled students should use Webcourses@UCF for slides, assignments, and announcements. For questions about enrolling or prerequisites, use the contact link.
Professional activities
- Editorial board
-
Associate Editor-in-Chief, IEEE Transactions on Computers, 2026 – present
Associate Editor, IEEE Transactions on Computers, 2025 – present
Associate Editor, IEEE Transactions on Sustainable Computing, 2025 – present - Program committees
- HPCA’27 · ISCA’26 (LPC) · MLSys’26 (ERC) · ICS’26 · ISPASS’25–26 · DAC’24–26 · ICCAD’24–25 · ICPP’25 · GLSVLSI’24 · IPDPS’23–24 · IISWC’23 · SRC@ASP-DAC’23 · HiPC’22 · NAS’22
- Organizing committees
- Finance Chair, ISCA’23 · Artifact Evaluation Co-Chair, IISWC’23 · Registration Chair, ICCD’23 · Local Arrangement Co-Chair, IPDPS’23 · Web Chair, HPCA’19
- NSF panels
- Panelist for multiple National Science Foundation programs.
- Journal reviewing
- IEEE Transactions on Computers · ACM/IEEE Transactions on Networking · IEEE Transactions on Cloud Computing · IEEE Transactions on Circuits and Systems II · IEEE Transactions on Sustainable Computing · IEEE Transactions on Very Large Scale Integration (VLSI) · IEEE Micro · IEEE Computer Architecture Letters · IEEE Transactions on Parallel and Distributed Systems · ACM Transactions on Architecture and Code Optimization (TACO) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · IEEE Transactions on Emerging Topics in Computing (TETC)
Review for IEEE Transactions on Computers
If you would like to serve as a reviewer for IEEE TC, please fill out the reviewer interest form.
Awards & honors
- 2026Inaugural ECE Excellence in Research Award, UCF
- 2026UCF Reach for the Stars AwardHighest university award for early-career faculty
- 2026GWU Technology Commercialization Office Innovation Award
- 2025NSF CAREER Award
- 2022ECE Best Dissertation Award, George Washington University
- 2020Best Paper Finalist, Design Automation Conference
- 2019First Place in ECE, SEAS R&D Showcase
- 2019First Place in Engineering, GWU Research Days
- 2019NSF GW I-Corps Site Grant Award
- 2018Dean Summer Award Fellowship
- 2018Second Place in Engineering, GWU Research Days
- 2017Phillip/Temofel Sprawcew Endowment Scholarship
News
A record of what the lab has been doing
Four papers accepted at MICRO ’26
KAIROS, Argus, DireLeak, and MOSAIC will appear in Athens.
TensorPrism accepted at ISCA ’26
Sparse high-order tensor acceleration via co-occurrence graphs.
PanGaea accepted at DAC ’26
A unified memory-efficient accelerator for pangenome chaining and alignment.
One paper accepted at HPCA ’26
Scaling graph neural network training via geometric optimization.
GAMMA accepted at NeurIPS ’25
Gated multi-hop message passing for homophily-agnostic node representation.
One paper accepted at MICRO ’25
Rethinking tiling and dataflow for SpMM acceleration.
DiTile-DGNN accepted at ISCA ’25
An accelerator for distributed dynamic GNN inference.
I-DGNN accepted at HPCA ’25
A graph dissimilarity-based framework for DGNN accelerators.
SCALE accepted at MICRO ’24
A structure-centric accelerator for message passing GNNs.
CircuitSeer accepted at ICCAD ’24
RTL post-PnR delay prediction.
MetaLeak accepted at ISCA ’24
Side channels in secure memory architectures.
EGMA and VITA accepted at DAC ’24
Two papers at the 61st Design Automation Conference.
Papers accepted at ISCA ’23, DAC ’23, and GLSVLSI ’23
Three papers accepted in the same season.
Chase and John received AMD Fellowships
Supporting their undergraduate research projects.
Two patents granted by the USPTO
US 11502934 and US 11489788.
Xilinx hardware donation
We received an equipment donation from Xilinx. Thank you, Xilinx.
L3Harris research grant
We received a grant from L3Harris, a leading aerospace and defense technology innovator. Thank you, L3Harris.
NVIDIA Academic Hardware Grant
Cloud credits from NVIDIA supporting our work on machine learning training. Thank you, NVIDIA.
TPC member, NAS 2022
Hao Zheng was invited to serve on the technical program committee for NAS 2022.
Three papers accepted at DATE ’22, TPDS, and TSUSC
- AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems — DATE 2022.
- SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing — IEEE TPDS, 2021.
- SecureNoC: A Learning-enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design — IEEE TSUSC, 2021.
Joined the ECE department at UCF
Starting the iCAT lab.